Virtual CPU Instruction Set: Porovnání verzí
Skočit na navigaci
Skočit na vyhledávání
Bez shrnutí editace |
Bez shrnutí editace |
||
| Řádek 1: | Řádek 1: | ||
==Design goals== |
==Design goals== |
||
* Simple to implement in |
* Simple to implement in other languages |
||
* Efficient to execute by emulator |
* Efficient to execute by emulator |
||
* Future extensibility (to support 128-bit data/address width or more) |
* Future extensibility (to support 128-bit data/address width or more) |
||
* Single code for any data/address width |
* Single instruction code for any data/address width |
||
* Register based load-store architecture rather than stack based machine or accumulator based machine |
|||
==Other interesting instruction sets== |
==Other interesting instruction sets== |
||
| Řádek 10: | Řádek 11: | ||
* [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set] |
* [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set] |
||
* [https://www.clear.rice.edu/elec422/1996/bomb/instrset.html MINI-CPU Instruction Set Specification] |
* [https://www.clear.rice.edu/elec422/1996/bomb/instrset.html MINI-CPU Instruction Set Specification] |
||
* [https://bartoszsypytkowski.com/simple-virtual-machine/ Simple Virtual Machine] |
|||
* [https://github.com/skx/simple.vm Simple virtual machine which inteprets bytecode.] |
|||
* [https://www.informatik-vollmer.de/software/vam-manual.pdf VAM Virtual Assembler Machine] |
|||
[[Category:Programování]] |
[[Category:Programování]] |
||
Verze z 15. 4. 2019, 13:01
Design goals
- Simple to implement in other languages
- Efficient to execute by emulator
- Future extensibility (to support 128-bit data/address width or more)
- Single instruction code for any data/address width
- Register based load-store architecture rather than stack based machine or accumulator based machine