Virtual CPU Instruction Set

Design goals

• Simple to implement in other programming languages
• Efficient to execute by emulator
• Future extensibility (to support 128-bit data/address width or more)
• Single instruction code for any data/address width
• Register based load-store architecture rather than stack based machine or accumulator based machine

Other interesting instruction sets

• Tiny CPU Instruction Set
• A Quick Introduction to the ZipCPU Instruction Set
• MINI-CPU Instruction Set Specification
• Simple Virtual Machine
• Simple virtual machine which inteprets bytecode.
• VAM Virtual Assembler Machine
• Simple 8-bit Assembler Simulator
• The RiSC-16 Instruction-Set Architecture