Virtual CPU Instruction Set: Porovnání verzí

Verze z 21. 12. 2019, 12:55

Simple to implement in other programming languages
Efficient to execute by emulator
Future extensibility (to support 128-bit data/address width or more)
Single instruction code for any data/address width
Register based load-store architecture rather than stack based machine or accumulator based machine

CPU	Instruction count	Instruction size [bits]	Data size [bits]	Addressable memory [bits]	Registers
Tiny CPU Instruction Set
A Quick Introduction to the ZipCPU Instruction Set	29	32	32	32	R0-R13, PC, CC
MINI-CPU Instruction Set Specification	12	4-12	8	8	PC, ACC, R
Simple Virtual Machine	18	8	32	32	PC, SP, FP
Simple virtual machine which interprets bytecode.
VAM Virtual Assembler Machine
Simple 8-bit Assembler Simulator	60	8	8	8	PC, SP, A, B, C, D
The RiSC-16 Instruction-Set Architecture	8	16	16	16	PC, R0-R7
TOY Machine	16	16	16	8 (256 words)	PC, R0-R15
MU0	8	16	16	12	PC, ACC
LC-3	15	16	16	16	PC, R0-R7
TOY/2 - a minimalist 16 bit CPU	15	16	16	16	PC, A, T
MARIE: An Introduction to a Simple Computer	9	16	16	12	PC, ACC
Building a 4-Bit Computer: The Instruction Set	16	4	4	12	R0-R5, S0, S1, PC, SP, IX, IV, TA
How to create your own virtual machine	35	8	8	16	A, B, X, Y, D
Little Man Computer	10	12	8	8	A

@@ Řádek 13: / Řádek 13: @@
 | [https://www.bigmessowires.com/2010/11/03/tiny-cpu-instruction-set/ Tiny CPU Instruction Set]
 |-
-| [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set]
+| [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set] || 29 || 32 || 32 || 32 || R0-R13, PC, CC
 |-
 | [https://www.clear.rice.edu/elec422/1996/bomb/instrset.html MINI-CPU Instruction Set Specification] || 12 || 4-12 || 8 || 8 || PC, ACC, R