Virtual CPU Instruction Set: Porovnání verzí
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! CPU !! Instruction count !! Instruction size [bits] !! Data size [bits] !! Addressable memory [bits] !! Registers |
! CPU !! Instruction count !! Instruction size [bits] !! Data size [bits] !! Addressable memory [bits] !! Registers |
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| [https://www.bigmessowires.com/2010/11/03/tiny-cpu-instruction-set/ Tiny CPU Instruction Set] |
| [https://www.bigmessowires.com/2010/11/03/tiny-cpu-instruction-set/ Tiny CPU Instruction Set] || 22 || 8-16 || 8 || 10 || PC, SP, A, X, SR |
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| [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set] || 29 || 32 || 32 || 32 || R0-R13, PC, CC |
| [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set] || 29 || 32 || 32 || 32 || R0-R13, PC, CC |
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| [https://github.com/skx/simple.vm Simple virtual machine which interprets bytecode.] || 36 || 16-32 || 16-32 || 16-32 || IP, FLAGS, R0-R9, SP |
| [https://github.com/skx/simple.vm Simple virtual machine which interprets bytecode.] || 36 || 16-32 || 16-32 || 16-32 || IP, FLAGS, R0-R9, SP |
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| [https://www.informatik-vollmer.de/software/vam-manual.pdf VAM Virtual Assembler Machine] |
| [https://www.informatik-vollmer.de/software/vam-manual.pdf VAM Virtual Assembler Machine] || 58 || 16-32 || 16-32 || 16-32 || R0-Rn (IP, SP) |
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| [https://schweigi.github.io/assembler-simulator/instruction-set.html Simple 8-bit Assembler Simulator] || 60 || 8 || 8 || 8 || PC, SP, A, B, C, D |
| [https://schweigi.github.io/assembler-simulator/instruction-set.html Simple 8-bit Assembler Simulator] || 60 || 8 || 8 || 8 || PC, SP, A, B, C, D |
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Verze z 14. 3. 2020, 21:35
Design goals
- Simple to implement in other programming languages
- Efficient to execute by emulator
- Future extensibility (to support 128-bit data/address width or more)
- Single instruction code for any data/address width
- Register based load-store architecture rather than stack based machine or accumulator based machine
Other interesting instruction sets
| CPU | Instruction count | Instruction size [bits] | Data size [bits] | Addressable memory [bits] | Registers |
|---|---|---|---|---|---|
| Tiny CPU Instruction Set | 22 | 8-16 | 8 | 10 | PC, SP, A, X, SR |
| A Quick Introduction to the ZipCPU Instruction Set | 29 | 32 | 32 | 32 | R0-R13, PC, CC |
| MINI-CPU Instruction Set Specification | 12 | 4-12 | 8 | 8 | PC, ACC, R |
| Simple Virtual Machine | 18 | 8 | 32 | 32 | PC, SP, FP |
| Simple virtual machine which interprets bytecode. | 36 | 16-32 | 16-32 | 16-32 | IP, FLAGS, R0-R9, SP |
| VAM Virtual Assembler Machine | 58 | 16-32 | 16-32 | 16-32 | R0-Rn (IP, SP) |
| Simple 8-bit Assembler Simulator | 60 | 8 | 8 | 8 | PC, SP, A, B, C, D |
| The RiSC-16 Instruction-Set Architecture | 8 | 16 | 16 | 16 | PC, R0-R7 |
| TOY Machine | 16 | 16 | 16 | 8 (256 words) | PC, R0-R15 |
| MU0 | 8 | 16 | 16 | 12 | PC, ACC |
| LC-3 | 15 | 16 | 16 | 16 | PC, R0-R7 |
| TOY/2 - a minimalist 16 bit CPU | 15 | 16 | 16 | 16 | PC, A, T |
| MARIE: An Introduction to a Simple Computer | 9 | 16 | 16 | 12 | PC, ACC |
| Building a 4-Bit Computer: The Instruction Set | 16 | 4 | 4 | 12 | R0-R5, S0, S1, PC, SP, IX, IV, TA |
| How to create your own virtual machine | 35 | 8 | 8 | 16 | A, B, X, Y, D |
| Little Man Computer | 10 | 12 | 8 | 8 | A |
| CRISC | 32 | struct | 64 | 16-64 |