Virtual CPU Instruction Set: Porovnání verzí
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==Design goals== |
==Design goals== |
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* Simple to implement in |
* Simple to implement in other languages |
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* Efficient to execute by emulator |
* Efficient to execute by emulator |
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* Future extensibility (to support 128-bit data/address width or more) |
* Future extensibility (to support 128-bit data/address width or more) |
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* Single code for any data/address width |
* Single instruction code for any data/address width |
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* Register based load-store architecture rather than stack based machine or accumulator based machine |
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==Other interesting instruction sets== |
==Other interesting instruction sets== |
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* [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set] |
* [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set] |
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* [https://www.clear.rice.edu/elec422/1996/bomb/instrset.html MINI-CPU Instruction Set Specification] |
* [https://www.clear.rice.edu/elec422/1996/bomb/instrset.html MINI-CPU Instruction Set Specification] |
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* [https://bartoszsypytkowski.com/simple-virtual-machine/ Simple Virtual Machine] |
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* [https://github.com/skx/simple.vm Simple virtual machine which inteprets bytecode.] |
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* [https://www.informatik-vollmer.de/software/vam-manual.pdf VAM Virtual Assembler Machine] |
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[[Category:Programování]] |
[[Category:Programování]] |
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Verze z 15. 4. 2019, 15:01
Design goals
- Simple to implement in other languages
- Efficient to execute by emulator
- Future extensibility (to support 128-bit data/address width or more)
- Single instruction code for any data/address width
- Register based load-store architecture rather than stack based machine or accumulator based machine