Virtual CPU Instruction Set: Porovnání verzí

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* [https://schweigi.github.io/assembler-simulator/instruction-set.html Simple 8-bit Assembler Simulator]
 
* [https://schweigi.github.io/assembler-simulator/instruction-set.html Simple 8-bit Assembler Simulator]
 
* [https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf The RiSC-16 Instruction-Set Architecture]
 
* [https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf The RiSC-16 Instruction-Set Architecture]
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* [https://introcs.cs.princeton.edu/java/62toy/ TOY Machine]
  
 
[[Category:Programování]]
 
[[Category:Programování]]

Verze z 11. 7. 2019, 15:31

Design goals

  • Simple to implement in other programming languages
  • Efficient to execute by emulator
  • Future extensibility (to support 128-bit data/address width or more)
  • Single instruction code for any data/address width
  • Register based load-store architecture rather than stack based machine or accumulator based machine

Other interesting instruction sets