Virtual CPU Instruction Set: Porovnání verzí

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Řádek 9: Řádek 9:
  
 
{| class="wikitable sortable"
 
{| class="wikitable sortable"
! CPU !! Instruction count !! Instruction size !! Data size !! Addressable memory !! Registers
+
! CPU !! Instruction count !! Instruction size [bits] !! Data size [bits] !! Addressable memory [bits] !! Registers
 
|-
 
|-
 
| [https://www.bigmessowires.com/2010/11/03/tiny-cpu-instruction-set/ Tiny CPU Instruction Set]
 
| [https://www.bigmessowires.com/2010/11/03/tiny-cpu-instruction-set/ Tiny CPU Instruction Set]
Řádek 15: Řádek 15:
 
| [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set]
 
| [https://zipcpu.com/zipcpu/2018/01/01/zipcpu-isa.html A Quick Introduction to the ZipCPU Instruction Set]
 
|-
 
|-
| [https://www.clear.rice.edu/elec422/1996/bomb/instrset.html MINI-CPU Instruction Set Specification]
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| [https://www.clear.rice.edu/elec422/1996/bomb/instrset.html MINI-CPU Instruction Set Specification] || 12 || 4-12 || 8 || 8 || PC, ACC, R
 
|-
 
|-
 
| [https://bartoszsypytkowski.com/simple-virtual-machine/ Simple Virtual Machine]
 
| [https://bartoszsypytkowski.com/simple-virtual-machine/ Simple Virtual Machine]
Řádek 27: Řádek 27:
 
| [https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf The RiSC-16 Instruction-Set Architecture]
 
| [https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf The RiSC-16 Instruction-Set Architecture]
 
|-
 
|-
| [https://introcs.cs.princeton.edu/java/62toy/ TOY Machine] || 16 || 16-bit || 16-bit || 8-bit (256 words) || PC, R0-R15
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| [https://introcs.cs.princeton.edu/java/62toy/ TOY Machine] || 16 || 16 || 16 || 8 (256 words) || PC, R0-R15
 
|-
 
|-
| [http://www.cs.man.ac.uk/~pjj/cs1001/arch/node2.html Instruction Execution on MU0] || 8 || 16-bit || 16-bit || 12-bit || PC, ACC
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| [http://www.cs.man.ac.uk/~pjj/cs1001/arch/node2.html Instruction Execution on MU0] || 8 || 16 || 16 || 12 || PC, ACC
 
|-
 
|-
| [https://en.wikipedia.org/wiki/LC-3 LC-3] || 15 || 16-bit || 16-bit || 16-bit || PC, R0-R7
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| [https://en.wikipedia.org/wiki/LC-3 LC-3] || 15 || 16 || 16 || 16 || PC, R0-R7
 
|}
 
|}
  
 
[[Category:Programování]]
 
[[Category:Programování]]

Verze z 19. 9. 2019, 09:55

Design goals[editovat]

  • Simple to implement in other programming languages
  • Efficient to execute by emulator
  • Future extensibility (to support 128-bit data/address width or more)
  • Single instruction code for any data/address width
  • Register based load-store architecture rather than stack based machine or accumulator based machine

Other interesting instruction sets[editovat]

CPU Instruction count Instruction size [bits] Data size [bits] Addressable memory [bits] Registers
Tiny CPU Instruction Set
A Quick Introduction to the ZipCPU Instruction Set
MINI-CPU Instruction Set Specification 12 4-12 8 8 PC, ACC, R
Simple Virtual Machine
Simple virtual machine which inteprets bytecode.
VAM Virtual Assembler Machine
Simple 8-bit Assembler Simulator
The RiSC-16 Instruction-Set Architecture
TOY Machine 16 16 16 8 (256 words) PC, R0-R15
Instruction Execution on MU0 8 16 16 12 PC, ACC
LC-3 15 16 16 16 PC, R0-R7