Virtual CPU Instruction Set: Porovnání verzí

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Řádek 25: Řádek 25:
 
| [https://schweigi.github.io/assembler-simulator/instruction-set.html Simple 8-bit Assembler Simulator] || 60 || 8 || 8 || 8 || PC, SP, A, B, C, D
 
| [https://schweigi.github.io/assembler-simulator/instruction-set.html Simple 8-bit Assembler Simulator] || 60 || 8 || 8 || 8 || PC, SP, A, B, C, D
 
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| [https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf The RiSC-16 Instruction-Set Architecture]
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| [https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf The RiSC-16 Instruction-Set Architecture] || 8 || 16 || 16 || 16 || PC, R0-R7
 
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| [https://introcs.cs.princeton.edu/java/62toy/ TOY Machine] || 16 || 16 || 16 || 8 (256 words) || PC, R0-R15
 
| [https://introcs.cs.princeton.edu/java/62toy/ TOY Machine] || 16 || 16 || 16 || 8 (256 words) || PC, R0-R15

Verze z 19. 9. 2019, 13:44

Design goals[editovat]

  • Simple to implement in other programming languages
  • Efficient to execute by emulator
  • Future extensibility (to support 128-bit data/address width or more)
  • Single instruction code for any data/address width
  • Register based load-store architecture rather than stack based machine or accumulator based machine

Other interesting instruction sets[editovat]

CPU Instruction count Instruction size [bits] Data size [bits] Addressable memory [bits] Registers
Tiny CPU Instruction Set
A Quick Introduction to the ZipCPU Instruction Set
MINI-CPU Instruction Set Specification 12 4-12 8 8 PC, ACC, R
Simple Virtual Machine 18 8 32 32 PC, SP, FP
Simple virtual machine which inteprets bytecode.
VAM Virtual Assembler Machine
Simple 8-bit Assembler Simulator 60 8 8 8 PC, SP, A, B, C, D
The RiSC-16 Instruction-Set Architecture 8 16 16 16 PC, R0-R7
TOY Machine 16 16 16 8 (256 words) PC, R0-R15
Instruction Execution on MU0 8 16 16 12 PC, ACC
LC-3 15 16 16 16 PC, R0-R7